Routing Events in Two-Dimensional Arrays with a Tree

Event: CVPR 2025 Workshop on Event-Based Vision · Duration: 36 min · ▶ Watch on YouTube

Abstract

Traditional row-column addressing schemes for event-based vision sensors suffer from race conditions, timing assumptions, and poor scaling with increasing array size. This work proposes a novel H-tree routing architecture that places the transceiver logic directly beneath the pixel array, eliminating wired-OR structures and their associated issues. The design utilizes a fully delay-insensitive asynchronous implementation with a bit-serial communication protocol, significantly reducing transistor count and improving scalability. While initial measurements showed lower throughput than simulation due to a layout error, the corrected design is projected to support large arrays with high event rates, demonstrating a promising approach for future high-performance event-based vision systems.

Speakers

  • Kwabena Boahen — Stanford University
  • Sam Fok — Femtosense Inc.

Talks (1)

  • 00:30 — Kwabena Boahen: Routing Events in Two-Dimensional Arrays with a Tree
    • This talk presents a novel H-tree routing architecture for event-based vision sensors, designed to efficiently route events in large 2D arrays while addressing limitations of traditional row-column addressing schemes.

Key Takeaways

  • Traditional row-column addressing for event-based sensors faces significant scaling challenges due to race conditions and timing assumptions.
  • The proposed H-tree routing architecture, with transceiver logic placed beneath the array, eliminates wired-ORs and their associated problems, leading to a more scalable design.
  • Utilizing a fully delay-insensitive asynchronous bit-serial communication protocol allows for efficient event routing and significant reduction in transistor count (13% to 45% savings compared to 2-ary trees).
  • The H-tree design effectively addresses critical path bottlenecks like column encoders by encoding addresses concurrently with arbitration, and prevents child request/parent grant race conditions.
  • Future improvements, including pipelining and bit-parallel communication, can further enhance throughput, potentially enabling 1024x1024 arrays at 730 events per second per pixel.

Methods / Models / Datasets Mentioned

  • Prophesee Event-Based Vision Sensor
  • Adaptive Delta Modulation (ADM)
  • Event Signal Processor (ESP)
  • BrainDrop Chip
  • 4-ary tree
  • Binary tree
  • Delay-Insensitive Serial Protocol
  • Communicating Hardware Processes (CHP)

Topics

Event-based vision · Asynchronous circuits · H-tree routing · 2D arrays · Delay-insensitive protocols · Neuromorphic engineering · Pixel array architecture · Throughput optimization · Transistor count reduction · Scalability

Notes

Open for commentary — connections to other work, critiques, follow-up reading.